HDLBits训练7

时间：2024.12.28

Fsm1

代码

module top_module(input clk,input areset,    // Asynchronous reset to state Binput in,output out);//  parameter A=0, B=1; reg state, next_state;always@(*)begincase(state)A:next_state=in?A:B;B:next_state=in?B:A;endcaseendalways @(posedge clk, posedge areset) begin    // This is a sequential always blockif(areset) state<=B;    // State flip-flops with asynchronous resetelse state<=next_state;end// Output logic// assign out = (state == ...);
assign out=state;
endmodule

运行结果

Tb/clock 

代码

module top_module ( );// 声明时钟信号reg clk;// 实例化dut模块dut dut_inst (.clk(clk));// 初始化时钟信号为0initial beginclk = 0;end// 产生时钟信号，周期为10 psalways begin#5 clk = ~clk;end
endmodule

运行结果

Tb/tb1

代码

module top_module ( output reg A, output reg B );//// generate input patterns hereinitial beginA=0;B=0;#10 A=1;#5 	B=1;#5 	A=0;#20	B=0;endendmodule

运行结果

Tb/and

 

代码

module top_module();reg[1:0] in;wire out;initialbeginin=2'b00;#10 in=2'b01;#10 in=2'b10;#10 in=2'b11;endandgate g1(in,out);endmodule

运行结果

 

Tb/tb2

代码

module top_module();parameter clk_period=10;reg clk;initial clk=0;always #(clk_period/2) clk=~clk;wire out;reg in;reg[2:0] s;initialbeginin=0;s=2;#10 s=6;#10 in=1;s=2;#10 in=0;s=7;#10 in=1;s=0;#30 in=0;endq7 inst_q7(clk,in,s,out);endmodule

运行结果

Tb/tff 

代码

    module top_module ();reg clk,t,q,reset;tff tff_1(.clk(clk),.reset(reset), .t(t),.q(q));initial beginclk=0;forever#5clk=~clk;endinitial beginreset = 1'b0;#3reset = 1'b1;#5reset = 1'b0;   endalways@(posedge clk)beginif(reset)begint <= 1'b0;endelse begint <= 1'b1;endendendmodule

运行结果

Bugs mux2 

代码

module top_module (input sel,input [7:0] a,input [7:0] b,output [7:0] out  );assign out =sel?a:b;endmodule

运行结果