用状态机写一个 LED流水灯的FPGA代码
采用分层结构，包括top文件，diplay文件，fenpin文件
编辑top文件
module LEDBlink(input wire clk, input wire rst_n, input wire key, output wire [5:0] led
);wire en_1hz; fenpin u_fenpin(.clk (clk),.rst_n (rst_n),.en (en_1hz)
);display u_display(.clk (clk),.rst_n (rst_n),.en (en_1hz),.key (key),.led (led)
);endmodule
编辑时钟
module fenpin(input wire clk, input wire rst_n,output reg en
);parameter CLK_FREQ = 50_000_000;
localparam CNT_MAX = CLK_FREQ - 1; reg [25:0] cnt; always @(posedge clk or negedge rst_n) beginif (!rst_n) begincnt <= 0;en <= 0;end else beginif (cnt == CNT_MAX) begincnt <= 0;en <= 1; end else begincnt <= cnt + 1;en <= 0;endend
endendmodule
编辑LED
module display(input wire clk,input wire rst_n,input wire en, input wire key, output reg [5:0] led
);reg [5:0] state;
reg pause_flag;
reg [2:0] key_sync;
wire key_negedge; always @(posedge clk or negedge rst_n) beginif (!rst_n) key_sync <= 3'b111;else key_sync <= {key_sync[1:0], key};
endassign key_negedge = (key_sync[2:1] == 2'b10);always @(posedge clk or negedge rst_n) beginif (!rst_n)pause_flag <= 0;else if (key_negedge)pause_flag <= ~pause_flag;
end
# 使用状态机的思想（通过 state 的移位实现状态流转）
always @(posedge clk or negedge rst_n) beginif (!rst_n) beginstate <= 6'b000001; end else if (en && !pause_flag) beginstate <= {state[4:0], state[5]}; end
endalways @(posedge clk) beginled <= state;
endendmodule
流水灯效果：
中断效果：
复位效果：
总结
天天学习。
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